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[討論] OMAP的新晶片??
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今天收到電子報...
TI出了新款的OMAP晶片...
順便就去他們的網頁看了一下....
幾個規格如下
ARM926TEJ
^^^^^^^^
從原本的ARM925變成ARM926TEJ, 不過還是屬於ARM9的指令集
TMS320C55x DSP core
^^^^^^^^^^^^^^^^
這個一樣, 沒有任何改變...還是同一顆DSP, 不過clock變成up to 204,
然後原本的16KB I-Cache及8KB D-Cache 整合成 24KB I-Cache
Hardware acceleration for Java, 2D graphics, audio, and security
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
這個在原本的OMAP1510中是完全沒有的, 不知道他們所謂的對Java的
硬體加速是怎樣的支援....尤其是以前就有聽說Palm的新機器要內建
Java支援,不免會令我想到, 說不定TT本來根本就是打算搭這個CPU...
其他的2D graphics, audio, and security也應該是大家都很重視的...
其他一些細部的東西不外乎是---更強大的省電功能,更快的時脈等...
不過有趣的是封裝是一樣的,不知道Palm能不能在只做小修改的情況
下把現有的TT的CPU換成OMAP1612...不過大概不太可能吧...
下面是規格...
-----------------------我是OMAP1612分隔線-----------------------
Low-voltage 130 nm technology
1.1 - 1.5V cores; 1.8 - 3.0V IO
Consumes less than 10 μA in standby mode
Split power supplies for application processing, digital baseband and real-time clock enable precise control over power consumption
Optimized clocking and power management: only two clocks required at 13 MHz and 32 kHz
TMS320C55x DSP core subsystem
Up to 204 MHz (maximum frequency)
32K x 16-bit on-chip dual-access RAM (DARAM) (64 KB)
48K x 16-bit on-chip single-access RAM (SARAM) (96 KB)
24 KB I-cache
One/two instructions executed per cycle
Video hardware accelerators for DCT, iDCT, pixel interpolation, and motion estimation for video compression
ARM926TEJ core subsystem
Up to 204 MHz ARM926TEJ V5 architecture (maximum frequency)
16KB I-cache; 8KB D-cache
Java acceleration
Support for 32-bit and 16-bit (thumb mode) instruction sets
Data and program MMUs
Two 64-entry translation look-aside buffers (TLBs) for MMUs
17-word write buffer
Security Acceleration in Hardware
Secure bootloader
48 kB of secure ROM
16 kB of secure RAM
Hardware acceleration for security standards and random number generator
Unique die ID cell
Third-party Security software library
Memory Traffic Controller (TC)
16-bit EMIFS external memory interface
16-bit EMIFF external memory interface
Mobile DDR and 128 Mb/256 Mb stacking memory options
Application Subsystem
Supports Linux, Microsoft Windows CE, Palm OS and Symbian OS, Microsoft Smartphone 2002, Microsoft Pocket PC 2002 and Nokia Series 60
OMAPI Standard compliant
DMA with 4 physical and 17 logical channels and a dedicated 2D graphics engine
USB On-the-Go (OTG)
Two SD/MMC/SDIO ports
Two high-speed 3.68 MHz UARTs
I2C controller
Two high-speed 3.68 MHz UARTs
uWire
CompactFlash
Parallel and compact camera ports
Enhanced Debug Trace (ETM) for debug
Fast IrDA (FIR)
SPI
LCD controller
Comprehensive memory controller for interfaces to:
128 MB of mobile SDRAM and mobile DDR
256 MB Flash (for burst, programmable NOR flash)
289-ball, 12 mm x 12 mm MicroStar BGA Package
-----------------------我是OMAP1510分隔線-----------------------
Low-Power, High-Performance CMOS Technology
Low-voltage 130 nm technology
TMS320C55x DSP Core
Up to 200 MHz (maximum frequency)
Voltage: 1.5v nominal
One/two instructions executed per cycle
32K x 16-bit on-chip dual-access RAM (DARAM) (64 KB)
48K x 16-bit on-chip single-access RAM (SARAM) (96 KB)
16 KB I-cache, 8 KB D-cache
Video hardware accelerators for DCT, iDCT, pixel interpolation, and motion estimation for video compression
TI925T ARM9TDMI Core
Up to 175 MHz (maximum frequency)
Voltage: 1.5v nominal
16KB I-cache; 8KB D-cache
192-KB of shared internal SRAM - frame buffer
Support for 32-bit and 16-bit (Thumb mode) instruction sets
Data and program MMUs
Two 64-entry translation look-aside buffers (TLBs) for MMUs
17-word write buffer
Memory Traffic Controller (TC)
16-bit EMIFS external memory interface
16-bit EMIFF external memory interface
9-Channel System DMA Controller
Digital Phase-Locked Loop (DPLL) for MPU/DSP/TC Clocking Control
Comprehensive Power-Saving Modes for MPU/DSP/TC
IEEE Standard 1149.1 (JTAG) Boundary Scan Logic
Application Subsystem
Supports Linux, Microsoft Windows CE, Palm OS and Symbian OS, Microsoft Smartphone 2002, Microsoft Pocket PC 2002 and Nokia Series 60
Three 32-bit timers and watchdog timer
32-kHz timer
Level1/Level2 interrupt handlers
USB1.1 host interface with up to 3 ports
USB1.1 function interface
One integrated USB transceiver for either host or function
Multichannel buffered serial port (McBSP)
I2C master and slave interface
Micro-wure serial interface
MMC/SD interface
HDQ/1-wire interface
Camera interface for CMOS sensors
ETM9 trace module for TI925T debug
Keyboard matrix interface (6 x 5 or 8 x 8)
Up to 10 MPU general-purpose I/Os
Pulse-width tone (PWT) interface
Pulse-width light (PWL) interface
Two LED pulse generators
Real-time clock
LCD controller with dedicated system DMA channel
Two multichannel buffered serial ports
Two multichannel serial interfaces
Three UARTs (one supporting SIR mode for IrDA)
Four interprocessor mailboxes
Up to 14 shared general-purpose I/Os
289-ball, 12 mm x 12 mm MicroStar BGA Package |
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狗仔卡
發表於 2003-2-22 00:16
顯身卡
發表於 2003-2-21 10:31
發表於 2003-2-21 11:11
